US 11,740,287 B2
Semiconductor device and semiconductor device examination method
Isao Ooigawa, Kawasaki Kanagawa (JP); Nariyuki Fukuda, Yokohama Kanagawa (JP); Kazuhito Hosaka, Kawasaki Kanagawa (JP); Tsutomu Miyamae, Yokohama Kanagawa (JP); Takeshi Yamaguchi, Kamakura Kanagawa (JP); Suguru Tahara, Yokohama Kanagawa (JP); Keitarou Mishima, Yokohama Kanagawa (JP); Yuichiro Sanuki, Urayasu Chiba (JP); and Koichi Kimura, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Toyko (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 9, 2022, as Appl. No. 17/690,443.
Claims priority of application No. 2021-147753 (JP), filed on Sep. 10, 2021.
Prior Publication US 2023/0079823 A1, Mar. 16, 2023
Int. Cl. G01R 31/3185 (2006.01)
CPC G01R 31/318536 (2013.01) [G01R 31/318541 (2013.01); G01R 31/318552 (2013.01); G01R 31/318555 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a plurality of scan chains each including a plurality of scan flip-flops;
a shift clock control circuit configured to output, to each of the plurality of scan chains, a control signal that non-inverts or inverts a scan clock signal; and
a shift clock generation circuit provided to each of the plurality of scan flip-flops and configured to generate a non-inverted scan clock signal or an inverted scan clock signal based on the control signal, the non-inverted scan clock signal being obtained by non-inverting the scan clock signal, the inverted scan clock signal being obtained by inverting the scan clock signal.