US 11,740,285 B2
Semiconductor integrated circuit device and operating method thereof
Yuusuke Takahashi, Kamakura Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Aug. 24, 2021, as Appl. No. 17/410,744.
Claims priority of application No. 2021-011674 (JP), filed on Jan. 28, 2021.
Prior Publication US 2022/0236324 A1, Jul. 28, 2022
Int. Cl. G01R 31/3177 (2006.01); G01R 31/317 (2006.01); G01R 31/3183 (2006.01); G01R 31/3187 (2006.01); G01R 31/3181 (2006.01); H01L 21/66 (2006.01); G01R 31/3193 (2006.01)
CPC G01R 31/3177 (2013.01) [G01R 31/3183 (2013.01); G01R 31/3187 (2013.01); G01R 31/3193 (2013.01); G01R 31/31703 (2013.01); G01R 31/31724 (2013.01); G01R 31/31727 (2013.01); G01R 31/31813 (2013.01); G01R 31/31932 (2013.01); G01R 31/31935 (2013.01); H01L 22/34 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit device, comprising:
a pattern generator configured to supply input data to a device-under-test;
a result comparator configured to compare output data from the device-under-test with expected value data and output a test result signal;
a control circuit that controls the pattern generator and the result comparator, wherein
the device-under-test and the result comparator are connected to a first clock line, and
the pattern generator and the control circuit are connected to a second clock line different from the first clock line,
the result comparator comprises:
an expected value comparison circuit configured to compare the output data of the device-under-test with the expected value data and output expected value comparison data;
a result holding circuit configured to hold the expected value comparison data from the expected value comparison circuit and output the test result signal; and
a second additional circuit connected to the first clock line and configured to receive a first signal related to the result holding circuit and output an additional circuit output signal, an initial state of the second additional circuit being a state in which the additional circuit output signal is output at a first signal level, and
the control circuit is further configured to:
determine that the test has not been performed normally if the additional circuit output signal from the result comparator is the first signal level at the end of the test,
determine that the test has been performed normally and that the device-under-test has passed the test if the additional circuit output signal from the result comparator is a second signal level different from the first signal level at the end of the test and the test result signal from the result comparator is the first signal level, and
determine that the test has been performed normally and that the device-under-test has failed the test if the additional circuit output signal from the result comparator is the second signal level at the end of the test and the test result signal from the result comparator is the second signal level.