US 12,400,967 B2
Embedded packaging structure and manufacturing method thereof
Xianming Chen, Jiangsu Province (CN); Lei Feng, Jiangsu Province (CN); Benxia Huang, Jiangsu Province (CN); Yue Bao, Jiangsu Province (CN); and Wenshi Wang, Jiangsu Province (CN)
Assigned to NANTONG ACCESS SEMICONDUCTOR CO., LTD., Jiangsu Province (CN)
Filed by Nantong ACCESS Semiconductor CO., LTD., Jiangsu Province (CN)
Filed on Mar. 10, 2022, as Appl. No. 17/691,403.
Claims priority of application No. 202110294274.6 (CN), filed on Mar. 19, 2021.
Prior Publication US 2022/0302037 A1, Sep. 22, 2022
Int. Cl. H01L 21/48 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H01L 25/10 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/5386 (2013.01) [H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/291 (2013.01); H01L 23/293 (2013.01); H01L 23/3121 (2013.01); H01L 25/0652 (2013.01); H01L 25/105 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 2224/16235 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method for manufacturing a multilayer embedded packaging structure, the method comprising:
(a) forming a first wiring layer on a temporary carrier plate, laminating a first dielectric layer on the first wiring layer, and thinning the first dielectric layer to expose the above-mentioned first wiring layer;
(b) forming a first copper pillar layer on the first dielectric layer, the first copper pillar layer comprising a sacrificial copper pillar, laminating a second dielectric layer on the first copper pillar layer, and thinning the second dielectric layer to expose the first copper pillar layer, the forming of the first copper pillar layer comprising:
(b1) forming a metal seed layer on the first dielectric layer;
(b2) applying a second photoresist layer on the metal seed layer of the first dielectric layer, and exposing and developing to form a second feature pattern;
(b3) performing electroplating in the second feature pattern to form an etch resist layer;
(b4) applying a third photoresist layer, and exposing and developing to form a third feature pattern;
(b5) performing electroplating in the third feature pattern to form a first copper pillar layer, and a sacrificial copper pillar on the etch resist layer, and removing the second photoresist layer and the third photoresist layer; and
(b6) laminating the second dielectric layer over the first feature layer and the sacrificial copper pillar, and thinning the second dielectric layer to expose the first feature layer and the sacrificial copper pillar;
(c) forming a second wiring layer on the second dielectric layer such that the first wiring layer and the second wiring layer are in conductive connection through the first copper pillar layer;
(d) forming a second copper pillar layer on the second wiring layer;
(e) etching the sacrificial copper pillar to form a device placement port frame exposing the first wiring layer; and
(f) removing the temporary carrier plate.