US 12,400,569 B2
Display device and electronic device
Munehiro Kozuma, Kanagawa (JP); Tatsuya Onuki, Kanagawa (JP); Takayuki Ikeda, Kanagawa (JP); and Takanori Matsuzaki, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Appl. No. 18/273,095
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
PCT Filed Jan. 17, 2022, PCT No. PCT/IB2022/050333
§ 371(c)(1), (2) Date Jul. 19, 2023,
PCT Pub. No. WO2022/162490, PCT Pub. Date Aug. 4, 2022.
Claims priority of application No. 2021-011834 (JP), filed on Jan. 28, 2021; application No. 2021-024802 (JP), filed on Feb. 19, 2021; and application No. 2021-028973 (JP), filed on Feb. 25, 2021.
Prior Publication US 2024/0090284 A1, Mar. 14, 2024
Int. Cl. G09G 3/20 (2006.01); G09G 3/3258 (2016.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01); H10K 59/80 (2023.01)
CPC G09G 3/20 (2013.01) [G09G 3/3258 (2013.01); H10K 59/1213 (2023.02); G09G 2300/0426 (2013.01); G09G 2310/0297 (2013.01); H10K 59/131 (2023.02); H10K 59/871 (2023.02); H10K 59/8722 (2023.02); H10K 59/873 (2023.02)] 4 Claims
OG exemplary drawing
 
1. A display device comprising:
a first layer;
a second layer positioned above the first layer; and
a third layer positioned above the second layer,
wherein the first layer comprises a driver circuit and a plurality of first wirings,
wherein the driver circuit comprises a plurality of output terminals positioned along a first direction,
wherein the plurality of output terminals are electrically connected to the plurality of first wirings,
wherein the plurality of first wirings are extended perpendicular to the first direction,
wherein the third layer comprises a pixel array and a plurality of second wirings,
wherein the pixel array comprises a plurality of pixel circuits arranged in a matrix,
wherein the plurality of pixel circuits are electrically connected to the plurality of second wirings,
wherein the plurality of second wirings are parallel to each other and extended in a column direction of the pixel array,
wherein the second layer comprises a plurality of first contact portions,
wherein the plurality of first wirings are electrically connected to the plurality of second wirings through the plurality of first contact portions, and
wherein the driver circuit is configured to control the plurality of pixel circuits.