US 12,069,967 B2
Integrated circuit including two substrates with qubits disposed within one of the two substrates
Christopher A. Cantaloube, Boca Raton, FL (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Jul. 12, 2022, as Appl. No. 17/863,213.
Application 17/863,213 is a division of application No. 16/858,812, filed on Apr. 27, 2020, granted, now 11,417,819.
Prior Publication US 2022/0352453 A1, Nov. 3, 2022
Int. Cl. H10N 60/81 (2023.01); H01L 23/00 (2006.01); H10N 60/01 (2023.01); H10N 60/12 (2023.01); H10N 60/80 (2023.01); H10N 69/00 (2023.01)
CPC H10N 60/815 (2023.02) [H01L 24/08 (2013.01); H01L 24/80 (2013.01); H10N 60/0912 (2023.02); H10N 60/12 (2023.02); H10N 60/805 (2023.02); H10N 69/00 (2023.02); H01L 2224/08146 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a first substrate having a plurality of conductive contact pads spaced apart from one another on a surface of the first substrate;
a dielectric layer overlying the first substrate and the plurality of conductive contact pads;
a second substrate overlying the dielectric layer, and
a plurality of superconducting contacts extending through the second substrate and the dielectric layer to the first substrate, wherein each superconducting contact of the plurality of superconducting contacts is aligned with and in contact with a respective conductive contact pad of the plurality of conductive contact pads, wherein the integrated circuit further comprises a first qubit and a second qubit disposed within the first substrate, wherein a first of the plurality of conductive contact pads is coupled to the first qubit and a second of the plurality of conductive contact pads is coupled to the second qubit.