CPC H10N 50/80 (2023.02) [G11C 11/161 (2013.01); H10B 61/00 (2023.02); H10N 50/01 (2023.02)] | 20 Claims |
1. A method comprising:
forming a memory stack over a substrate;
depositing a dielectric layer to cover the memory stack;
forming an opening in the dielectric layer, wherein the opening does not expose the memory stack;
forming a spin-orbit-torque (SOT) layer in the opening; and
forming a free layer over the dielectric layer to interconnect the memory stack and the SOT layer.
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