US 12,069,958 B2
Semiconductor device
Tai-Yen Peng, Hsinchu (TW); Hui-Hsien Wei, Taoyuan (TW); Wei-Chih Wen, Hsinchu County (TW); Pin-Ren Dai, Hsinchu County (TW); Chien-Min Lee, Hsinchu County (TW); Sheng-Chih Lai, Hsinchu County (TW); Han-Ting Tsai, Kaohsiung (TW); and Chung-Te Lin, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on May 4, 2023, as Appl. No. 18/312,372.
Application 18/312,372 is a continuation of application No. 17/221,674, filed on Apr. 2, 2021, granted, now 11,683,988.
Application 17/221,674 is a continuation of application No. 16/866,101, filed on May 4, 2020, granted, now 10,971,682, issued on Apr. 6, 2021.
Application 16/866,101 is a continuation of application No. 15/828,101, filed on Nov. 30, 2017, granted, now 10,644,231, issued on May 5, 2020.
Prior Publication US 2023/0276712 A1, Aug. 31, 2023
Int. Cl. H10N 50/01 (2023.01); G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01)
CPC H10N 50/01 (2023.02) [G11C 11/161 (2013.01); H10B 61/20 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a resistance switching layer over a substrate;
a capping layer over the resistance switching layer;
a top electrode over the capping layer;
a first spacer lining the resistance switching layer and the capping layer; and
a second spacer lining the first spacer, wherein the capping layer is in contact with the top electrode, the first spacer, and the second spacer.