US 12,069,907 B2
Display panel and display device
Lijing Han, Shanghai (CN); Xian Chen, Shanghai (CN); and Yu Xin, Shanghai (CN)
Assigned to WUHAN TIANMA MICRO-ELECTRONICS CO., LTD., Wuhan (CN); and WUHAN TIANMA MICROELECTRONICS CO., LTD. SHANGHAI BRANCH, Shanghai (CN)
Filed by WUHAN TIANMA MICRO-ELECTRONICS CO., LTD., Wuhan (CN)
Filed on Apr. 18, 2023, as Appl. No. 18/302,216.
Application 18/302,216 is a continuation of application No. 17/473,361, filed on Sep. 13, 2021, granted, now 11,690,260.
Application 17/473,361 is a continuation of application No. 16/358,924, filed on Mar. 20, 2019, granted, now 11,152,445, issued on Oct. 19, 2021.
Claims priority of application No. 201811404221.X (CN), filed on Nov. 23, 2018.
Prior Publication US 2023/0371320 A1, Nov. 16, 2023
Int. Cl. H10K 59/126 (2023.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01)
CPC H10K 59/126 (2023.02) [H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/131 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A display panel, comprising:
a plurality of pixel circuits arranged in a matrix; and
a blocking unit,
wherein each of the plurality of pixel circuits comprises:
a driving transistor having a gate electrode and a first electrode;
a first switch transistor having a gate electrode electrically connected to a first scanning signal line, a first electrode electrically connected to a reference voltage signal line, and a second electrode electrically connected to the gate electrode of the driving transistor;
a second switch transistor, having a gate electrode electrically connected to a second scanning signal line, a first electrode electrically connected to a data line, and a second electrode electrically connected to the first electrode of the driving transistor; and
a third switch transistor having a gate electrode electrically connected to a light-emitting control signal line, a first electrode electrically connected to a power supply voltage signal line, and a second electrode electrically connected to the first electrode of the driving transistor,
wherein the blocking unit is configured to receive a fixed potential signal, and at least a partial area of the blocking unit is located between a first semiconductor connection portion and a second semiconductor connection portion, the first semiconductor connection portion is a semiconductor electrically connected between the second electrode of the first switch transistor and the gate electrode of the driving transistor, and the second semiconductor connection portion is a semiconductor electrically connected between the first electrode of the second switch transistor and the data line, and
wherein the power supply voltage signal line at least partially overlaps with the gate electrode of the driving transistor and at least partially overlaps a semiconductor connection portion located between the second switch transistor and the third switch transistor.