US 12,069,876 B2
Semiconductor device and electronic device
Koji Kusunoki, Kanagawa (JP); Kazunori Watanabe, Tokyo (JP); Tomoaki Atsumi, Kanagawa (JP); and Satoshi Yoshimoto, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 18/546,685
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
PCT Filed Feb. 14, 2022, PCT No. PCT/IB2022/051271
§ 371(c)(1), (2) Date Aug. 16, 2023,
PCT Pub. No. WO2022/180480, PCT Pub. Date Sep. 1, 2022.
Claims priority of application No. 2021-028671 (JP), filed on Feb. 25, 2021.
Prior Publication US 2024/0138169 A1, Apr. 25, 2024
Prior Publication US 2024/0237376 A9, Jul. 11, 2024
Int. Cl. G02F 1/1333 (2006.01); G06F 3/042 (2006.01); G06V 40/13 (2022.01); G09G 3/3233 (2016.01); H10K 39/34 (2023.01); H10K 59/131 (2023.01)
CPC H10K 39/34 (2023.02) [G06F 3/042 (2013.01); G06V 40/1318 (2022.01); G09G 3/3233 (2013.01); H10K 59/131 (2023.02); G06F 2203/04108 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2354/00 (2013.01); G09G 2360/14 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a plurality of pixels,
wherein the pixels each comprise a first pixel circuit,
wherein the first pixel circuit comprises a first light-receiving device, a second light-receiving device, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a capacitor, and a first wiring,
wherein one electrode of the first light-receiving device is electrically connected to the first wiring,
wherein the other electrode of the first light-receiving device is electrically connected to one of a source and a drain of the first transistor,
wherein one electrode of the second light-receiving device is electrically connected to the first wiring,
wherein the other electrode of the second light-receiving device is electrically connected to one of a source and a drain of the second transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the fourth transistor, and
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor.