US 12,069,866 B2
Pocket integration process for embedded memory
Noriyuki Sato, Hillsboro, OR (US); Tanay Gosavi, Portland, OR (US); Niloy Mukherjee, San Ramon, CA (US); Amrita Mathuriya, Portland, OR (US); Rajeev Kumar Dokania, Beaverton, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing, Inc., San Francisco, CA (US)
Filed on Sep. 2, 2021, as Appl. No. 17/465,792.
Prior Publication US 2023/0067612 A1, Mar. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 53/30 (2023.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01); H01L 49/02 (2006.01); H03K 19/185 (2006.01); H10B 53/10 (2023.01); H10B 53/40 (2023.01)
CPC H10B 53/30 (2023.02) [H01L 21/76802 (2013.01); H01L 23/528 (2013.01); H01L 23/53209 (2013.01); H01L 23/53228 (2013.01); H01L 23/53242 (2013.01); H01L 23/53257 (2013.01); H01L 23/535 (2013.01); H01L 28/55 (2013.01); H01L 28/60 (2013.01); H01L 28/65 (2013.01); H03K 19/185 (2013.01); H10B 53/10 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A device comprising:
a first region comprising:
a plurality of first conductive interconnects within a first level; and
a second level above the first level, the second level comprising:
a plurality of ferroelectric memory devices, wherein an individual ferroelectric memory device in the plurality of ferroelectric memory devices is above a respective first conductive interconnect in the plurality of first conductive interconnects, and wherein the individual ferroelectric memory device in the plurality of ferroelectric memory devices comprises a first height;
an encapsulation layer on a sidewall of the individual ferroelectric memory device in the plurality of ferroelectric memory devices, wherein the encapsulation layer extends below a lowermost surface of the individual ferroelectric memory device; and
a via electrode on the individual ferroelectric memory device in the plurality of ferroelectric memory devices, wherein the via electrode comprises a second height; and
a second region adjacent to the first region, the second region comprising an interconnect structure, the interconnect structure comprising:
one or more second conductive interconnects within the first level;
an etch stop layer comprising a dielectric material in the second level, wherein the dielectric material is different from a material of the encapsulation layer;
a plurality of metal lines above the etch stop layer, wherein the plurality of metal lines is within the second level, and wherein a respective individual metal line in the plurality of metal lines comprises a third height; and
a via structure coupling a metal line in the plurality of metal lines with a second conductive interconnect in the one or more second conductive interconnects, wherein the via structure is in the second level and comprises a fourth height, and wherein a combined sum of the first height and the second height is equal to a combined sum of the third height and the fourth height.