US 12,069,864 B2
Memory array and methods of forming same
Yu-Ming Lin, Hsinchu (TW); Bo-Feng Young, Taipei (TW); Sai-Hooi Yeong, Zhubei (TW); Han-Jong Chia, Hsinchu (TW); and Chi On Chui, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Feb. 26, 2021, as Appl. No. 17/186,852.
Claims priority of provisional application 63/148,639, filed on Feb. 12, 2021.
Prior Publication US 2022/0262809 A1, Aug. 18, 2022
Int. Cl. H10B 51/30 (2023.01); G11C 8/14 (2006.01); H10B 51/10 (2023.01); H10B 51/20 (2023.01)
CPC H10B 51/30 (2023.02) [G11C 8/14 (2013.01); H10B 51/10 (2023.02); H10B 51/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a semiconductor substrate;
a first word line over the semiconductor substrate, the first word line providing a first gate electrode for a first transistor;
a second word line over the first word line, the second word line being insulated from the first word line by a first dielectric material, the second word line providing a second gate electrode for a second transistor over the first transistor;
a source line intersecting the first word line and the second word line;
a bit line intersecting the first word line and the second word line, the bit line being insulated from the source line by a second dielectric material;
a memory film between the first word line and the source line, the memory film further being disposed between the first word line and the bit line, wherein the memory film further extends directly under the bit line; and
a first semiconductor material between the memory film and the source line, the first semiconductor material further being disposed between the first word line and the source line, wherein the first semiconductor material further extends directly under the bit line.