US 12,069,860 B2
Semiconductor device and manufacturing method of semiconductor device
Yoo Hyun Noh, Icheon-si (KR); and Da Yung Byun, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Feb. 16, 2023, as Appl. No. 18/110,604.
Application 18/110,604 is a continuation of application No. 17/062,223, filed on Oct. 2, 2020, granted, now 11,610,913.
Claims priority of application No. 10-2020-0054722 (KR), filed on May 7, 2020.
Prior Publication US 2023/0200064 A1, Jun. 22, 2023
Int. Cl. H10B 43/20 (2023.01); H01L 23/522 (2006.01); H10B 41/20 (2023.01); H10B 41/40 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/20 (2023.02) [H01L 23/5226 (2013.01); H10B 41/20 (2023.02); H10B 41/40 (2023.02); H10B 43/40 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming a stacked structure including sacrificial layers and insulating layers stacked alternately with each other;
forming a first slit passing through the stacked structure;
forming a second slit passing through the stacked structure and spaced apart from the first slit;
forming first openings coupling the first slit and the second slit to each other by etching sacrificial layers exposed through the first slit and the second slit;
forming a slit structure in the first slit, the second slit, and the first openings;
forming second openings by selectively removing the sacrificial layers located at one side of the slit structure; and
forming conductive layers in the second openings.