US 12,069,858 B2
Three-dimensional semiconductor memory device
Woosung Yang, Gwangmyeong-si (KR); Byungjin Lee, Hwaseong-si (KR); Bumkyu Kang, Suwon-si (KR); and Dong-Sik Lee, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 31, 2023, as Appl. No. 18/194,258.
Application 18/194,258 is a continuation of application No. 17/021,416, filed on Sep. 15, 2020, granted, now 11,641,738.
Claims priority of application No. 10-2020-0005350 (KR), filed on Jan. 15, 2020.
Prior Publication US 2023/0240068 A1, Jul. 27, 2023
Int. Cl. H10B 41/20 (2023.01); G11C 7/18 (2006.01); G11C 16/08 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/46 (2023.01); H10B 41/48 (2023.01); H10B 43/10 (2023.01); H10B 43/20 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H10B 41/46 (2023.02) [G11C 7/18 (2013.01); G11C 16/08 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/20 (2023.02); H10B 41/48 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional semiconductor memory device, comprising:
a first peripheral circuit including a plurality of different decoder circuits;
a first memory on the first peripheral circuit, the first memory including
a first stack structure having a plurality of first electrode layers stacked on one another and a plurality of first inter-electrode dielectric layers between first electrode layers of the plurality of first electrode layers, and
a first through via that penetrates an end of the first stack structure, the first through via being insulated from the plurality of first electrode layers and electrically connected to one of the plurality of different decoder circuits; and
a second memory on the first memory, the second memory including
a second stack structure having a plurality of second electrode layers stacked on one another and a plurality of second inter-electrode dielectric layers between second electrode layers of the plurality of second electrode layers, and
a first cell contact plug electrically connecting one of the plurality of second electrode layers to the first through via.