| CPC H10B 41/27 (2023.02) [G11C 5/06 (2013.01); G11C 16/0408 (2013.01); G11C 16/0466 (2013.01); H10B 43/27 (2023.02)] | 18 Claims |
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1. A semiconductor memory comprising:
a semiconductor substrate;
a control circuit provided on the semiconductor substrate in a first region and a second region;
a first layer provided above the control circuit in the first region and the second region, the first layer in the first region functioning as a source line;
a stacked body including a plurality of first insulating layers and a plurality of first conductive layers alternately stacked in a first direction above the first layer in the first region, the plurality of first conductive layers not existing in the second region;
a pillar including a first semiconductor layer and extending in the first direction through the stacked body, a first end of the first semiconductor layer being provided within the source line; and
a through-contact extending in the first direction through the first layer in the second region, the through-contact being electrically connected to the control circuit,
wherein the first layer comprises a first portion in the first region and a second portion in the second region,
the first portion includes a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer in order in the first direction,
the second portion includes the second semiconductor layer, a second insulating layer, a second layer containing silicon, a third insulating layer, and the fourth semiconductor layer in order in the first direction, and
the second layer is at a same layer level as the third semiconductor layer and is formed of a different material from a material of the third semiconductor layer,
wherein the first portion includes the second semiconductor layer, the second insulating layer, the third semiconductor layer, the third insulating layer, and the fourth semiconductor layer in order in the first direction.
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