CPC H10B 41/20 (2023.02) [H01L 25/0652 (2013.01); H10B 41/41 (2023.02); H10B 43/20 (2023.02); H10B 43/40 (2023.02)] | 20 Claims |
1. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising:
a first semiconductor layer;
an array of NAND memory strings on a first side of the first semiconductor layer; and
a first peripheral circuit comprising a first transistor in contact with a second side of the first semiconductor layer opposite to the first side,
wherein the first semiconductor layer functions as a source line of array of NAND memory strings and a channel of the first transistor;
a second semiconductor structure comprising:
a second semiconductor layer; and
a second peripheral circuit comprising a second transistor in contact with the second semiconductor layer; and
a bonding interface between the first semiconductor structure and the second semiconductor structure.
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