US 12,069,854 B2
Three-dimensional memory devices and methods for forming the same
Kun Zhang, Wuhan (CN); Yuancheng Yang, Wuhan (CN); Wenxi Zhou, Wuhan (CN); Wei Liu, Wuhan (CN); Zhiliang Xia, Wuhan (CN); Liang Chen, Wuhan (CN); and Yanhong Wang, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Sep. 21, 2021, as Appl. No. 17/480,998.
Application 17/480,998 is a continuation of application No. PCT/CN2021/103762, filed on Jun. 30, 2021.
Prior Publication US 2023/0005943 A1, Jan. 5, 2023
Int. Cl. H10B 41/20 (2023.01); H01L 25/065 (2023.01); H10B 41/41 (2023.01); H10B 43/20 (2023.01); H10B 43/40 (2023.01)
CPC H10B 41/20 (2023.02) [H01L 25/0652 (2013.01); H10B 41/41 (2023.02); H10B 43/20 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising:
a first semiconductor layer;
an array of NAND memory strings on a first side of the first semiconductor layer; and
a first peripheral circuit comprising a first transistor in contact with a second side of the first semiconductor layer opposite to the first side,
wherein the first semiconductor layer functions as a source line of array of NAND memory strings and a channel of the first transistor;
a second semiconductor structure comprising:
a second semiconductor layer; and
a second peripheral circuit comprising a second transistor in contact with the second semiconductor layer; and
a bonding interface between the first semiconductor structure and the second semiconductor structure.