US 12,069,853 B2
Memory device having shared access line for 2-transistor vertical memory cell
Kamal M. Karda, Boise, ID (US); Karthik Sarpatwari, Boise, ID (US); Durai Vishak Nirmal Ramaswamy, Boise, ID (US); and Haitao Liu, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 4, 2022, as Appl. No. 17/712,674.
Application 17/712,674 is a division of application No. 16/725,439, filed on Dec. 23, 2019, granted, now 11,296,094.
Claims priority of provisional application 62/785,150, filed on Dec. 26, 2018.
Prior Publication US 2022/0223605 A1, Jul. 14, 2022
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/50 (2023.02) [H10B 12/01 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first transistor of a memory cell, including forming a charge storage structure over a substrate, and forming a first channel region from a portion of a semiconductor material, the first channel region separated from the charge storage structure by a dielectric material between the portion of the semiconductor material and the charge storage structure;
forming a second transistor of the memory cell, including forming a second channel region directly on the charge storage structure and separated from the first channel region by the dielectric material;
forming a first data line coupled to the first channel region; and
forming a second data line coupled to the first channel region, wherein the first and second data lines are formed after the first channel region is formed.