US 12,069,851 B2
Transistor, memory and method of forming same
Chung-Yen Chou, Fujian (CN); Chih-Yuan Chen, Fujian (CN); Qinfu Zhang, Fujian (CN); Chao-Wei Lin, Fujian (CN); Chia-Yi Chu, Fujian (CN); Jen-Chieh Cheng, Fujian (CN); Jen-Kuo Wu, Fujian (CN); and Huixian Lai, Fujian (CN)
Assigned to Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou (CN)
Appl. No. 17/298,315
Filed by FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD., Fujian (CN)
PCT Filed Mar. 17, 2020, PCT No. PCT/CN2020/079583
§ 371(c)(1), (2) Date May 28, 2021,
PCT Pub. No. WO2021/022812, PCT Pub. Date Feb. 11, 2021.
Claims priority of application No. 201910759563.1 (CN), filed on Aug. 16, 2019; and application No. 201910833563.1 (CN), filed on Sep. 4, 2019.
Prior Publication US 2022/0028867 A1, Jan. 27, 2022
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/488 (2023.02) [H10B 12/34 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A device, comprising:
a substrate with a trench therein;
a gate dielectric layer covering an inner surface of the trench,
a gate conductive layer over the gate dielectric layer and within the trench, wherein a top surface of the gate conductive layer is lower than a top surface of the gate dielectric layer; and
an insulating dielectric layer on the gate conductive layer;
a cover layer covering a side surface of the gate dielectric layer away from the trench, wherein the cover layer provided among of the gate dielectric layer, the gate conductive layer and the insulating dielectric layer, and directly contact with the gate dielectric layer, the gate conductive layer and the insulating dielectric layer mutually.