US 12,069,850 B2
Semiconductor structure, manufacturing method thereof, and memory having bit line conducting layers covering the bit line contact layer and the insulating layer
Chih-Cheng Liu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Nov. 10, 2021, as Appl. No. 17/523,084.
Application 17/523,084 is a continuation of application No. PCT/CN2021/109353, filed on Jul. 29, 2021.
Claims priority of application No. 202011104467.2 (CN), filed on Oct. 15, 2020; and application No. 202110083678.0 (CN), filed on Jan. 21, 2021.
Prior Publication US 2022/0122990 A1, Apr. 21, 2022
Int. Cl. H01B 12/00 (2006.01); H10B 12/00 (2023.01)
CPC H10B 12/485 (2023.02) [H10B 12/34 (2023.02); H10B 12/482 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate, wherein a plurality of active areas arranged in an array are provided in the substrate;
buried word lines, located in the substrate, wherein each of the active areas intersects with two of the buried word lines;
grooves, located in an upper surface of the substrate, wherein each of the grooves is located between two of the buried word lines in each of the active areas;
bit line contact layers, filling the grooves;
insulating layers, distributed between two of the grooves, wherein a thickness between upper surfaces of the insulating layers and the upper surface of the substrate is smaller than a thickness between upper surfaces of the bit line contact layers and the upper surface of the substrate; and
bit line conducting layers, covering the bit line contact layers and the insulating layers.