US 12,069,636 B2
Scrambling for control messages
Debdeep Chatterjee, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/359,465.
Application 17/359,465 is a continuation of application No. 16/095,667, granted, now 11,051,306, previously published as PCT/US2016/064822, filed on Dec. 2, 2016.
Claims priority of provisional application 62/336,389, filed on May 13, 2016.
Prior Publication US 2021/0329641 A1, Oct. 21, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H04W 72/044 (2023.01); H04L 1/00 (2006.01); H04L 5/00 (2006.01); H04W 72/23 (2023.01); H04W 88/02 (2009.01)
CPC H04W 72/0466 (2013.01) [H04L 1/004 (2013.01); H04L 5/0053 (2013.01); H04W 72/23 (2023.01); H04W 88/02 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus of a bandwidth-reduced low complexity (BL) user equipment (UE) or a coverage enhancement (CE) UE comprising one or more processors to:
determine a number of subframes Nacc in a given block of Nacc subframes of a physical downlink shared channel (PDSCH); and
decode the PDSCH, wherein the PDSCH includes scrambled coded bits scrambled with a scrambling sequence initialized with an initialization value cinit, wherein the scrambling sequence is applied per subframe to the PDSCH for the given block of Nacc subframes, wherein:
Nacc is set to 1 when the scrambled coded bits to be transmitted via the PDSCH form a system information block type 1 (SIB1) bandwidth reduced (BR); and
Nacc is set to 4 for a frame structure type 1 and Nacc is set to 10 for a frame structure type 2, when the scrambled coded bits to be transmitted via the PDSCH form a type of system information (SI) message other than a system information block type 1 (SIB1) bandwidth reduced (BR).