| CPC H04N 25/46 (2023.01) [H04N 23/84 (2023.01); H04N 25/772 (2023.01)] | 19 Claims |
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1. An electronic device, comprising:
a pixel array configured to output a raw image including a plurality of color pixels and a plurality of specific pixels;
a logic circuit configured to output a first binned image by performing first binning on pixels among the color pixels and the specific pixels in a column direction for each of a plurality of unit kernels of the raw image; and
a processor configured to output a second binned image by performing second binning on the first binned image,
wherein, when a unit kernel among the unit kernels includes at least one of the specific pixels, a column to which the at least one specific pixel belongs is read out at a readout timing different from a readout timing of a column to which none of the specific pixels belong and undergoes the first binning, and
the second binning combines a binned color pixel value of the column to which none of the specific pixels belong with a corrected color pixel value of the column to which the at least one specific pixel belongs,
wherein the processor generates the binned color pixel value by performing binning on color pixels of the column to which none of the specific pixels belong in a row direction, and generates the corrected color pixel value by correcting the column to which the at least one specific pixel belongs to an adjacent color pixel value in the row direction,
wherein the first binned image of the column to which the at least one specific pixel belongs includes the corrected color pixel value.
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