CPC H04N 19/597 (2014.11) [G06T 5/80 (2024.01); H04N 19/159 (2014.11); H04N 19/176 (2014.11); H04N 19/46 (2014.11); H04N 19/85 (2014.11)] | 2 Claims |
1. A decoder, comprising:
processing circuitry; and
memory connected to the processing circuitry,
wherein, using the memory, the processing circuitry:
performs an inter prediction process on a first picture, the first picture including a plurality of regions, wherein
the inter prediction process includes an arrangement process in which a plurality of pixels within the first picture is arranged or rearranged in a way in which an object within neighboring regions among the plurality of regions is continuous.
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