CPC H04L 63/0815 (2013.01) [G06F 9/451 (2018.02)] | 20 Claims |
1. A computer-implemented method comprising:
obtaining information pertaining to a container-orchestration system operating within at least one cloud native environment;
configuring, based at least in part on the obtained information, a single sign-on authentication mechanism for multiple user interface applications in the container-orchestration system;
configuring, based at least in part on the obtained information, at least one ingress route for two or more of the multiple user interface applications in the container-orchestration system, wherein configuring at least one ingress route comprises automatically defining one or more reverse proxy rules and one or more transport layer security techniques for encrypting traffic for the at least one ingress route in the container-orchestration system;
configuring and rendering, based at least in part on information pertaining to the at least one ingress route, a common header in each of the two or more user interface applications, wherein configuring the common header is based at least in part on metadata pertaining to the at least one ingress route derived from at least one container-orchestration system configuration map, and wherein configuring the common header comprises reading at least a portion of the metadata pertaining to the at least one ingress route derived from the at least one container-orchestration system configuration map; returning a navigation map, at page load time, to one or more code segments in a programming language, the one or more code segments included in each of the two or more user interface applications; and replacing at least one hypertext markup language placeholder in the one or more code segments; and
performing one or more automated actions based at least in part on the configured single sign-on authentication mechanism, the at least one configured ingress route, and the configured and rendered common header;
wherein the method is performed by at least one processing device comprising a processor coupled to a memory.
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