| CPC H04L 5/0098 (2013.01) [H04L 5/0005 (2013.01); H04L 5/0044 (2013.01); H04W 36/06 (2013.01); H04W 72/0453 (2013.01)] | 9 Claims |
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1. An apparatus, comprising;
at least one processor; and
at least one memory including computer program code, the at least one memory and computer program code being configured, with the at least one processor, to cause the apparatus to perform:
first monitoring if a first packet data unit is received from a sender on a first active bandwidth part of a carrier at a first reception time;
determining a delay and a second bandwidth part of the carrier based on a switching rule; wherein
the switching rule defines that the second bandwidth part is different from the first bandwidth part; and
the first monitoring is configured to monitor, if the first packet data unit is received, if a second packet data unit is received from the sender on the second active bandwidth part at a second reception time after the delay after the first packet data unit was received has elapsed; wherein
the first packet data unit has a first sequence number;
the second packet data unit has a second sequence number; and wherein the at least one memory and computer program code are further configured, with the at least one processor, to cause the apparatus to perform first checking if the first sequence number is the same as the second sequence number; and
handling the second packet data unit as a duplicate of the first packet data unit if the first sequence number is the same as the second sequence number; and
wherein the at least one memory and computer program code are further configured, with the at least one processor, to cause the apparatus to perform supervising if an information is received that the sender duplicates a received packet data unit into the first packet data unit and the second packet data unit; and inhibiting the first checking from checking if the information is not received.
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