CPC H04L 5/0053 (2013.01) [H04W 56/001 (2013.01)] | 26 Claims |
1. An apparatus for wireless communication, comprising:
one or more processors,
memory coupled with the one or more processors, and
instructions stored in the memory and executable by the one or more processors to cause the apparatus to:
receive at a first frequency a synchronization signal block that indicates a second frequency of a control resource set relative to the synchronization signal block, wherein the second frequency is based at least in part on one or more of: an offset associated with a control resource set bandwidth, a combination of a first parameter associated with a first portion of the synchronization signal block and a second parameter associated with a second portion of the synchronization signal block, or both;
receive an indication of a frequency offset, wherein the frequency offset comprises the offset associated with the control resource set bandwidth;
determine the second frequency based at least in part on the first frequency and the received frequency offset;
receive at the first frequency a second synchronization signal block, wherein the second synchronization signal block indicates a third frequency of a second control resource set relative to the second synchronization signal block, wherein the control resource set bandwidth comprises a bandwidth of the second control resource set;
monitor the control resource set at the indicated second frequency for a downlink control channel transmission; and
receive system information based at least in part on the downlink control channel transmission.
|