US 12,068,893 B2
Two-dimensional high-speed equalizer with programmable direct current (DC) and peaking gains
Xueyang Geng, Chandler, AZ (US); Xu Zhang, Chandler, AZ (US); Xiaoqun Liu, Chandler, AZ (US); and Siamak Delshadpour, Phoenix, AZ (US)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Dec. 21, 2022, as Appl. No. 18/069,664.
Prior Publication US 2024/0223411 A1, Jul. 4, 2024
Int. Cl. H04L 25/03 (2006.01); H03F 3/45 (2006.01); H03K 17/60 (2006.01); H03K 17/687 (2006.01)
CPC H04L 25/03878 (2013.01) [H03F 3/45076 (2013.01); H03K 17/60 (2013.01); H03K 17/687 (2013.01); H03F 2203/45458 (2013.01); H03F 2203/45496 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An equalizer comprising:
a first signal path segment that comprises a first plurality of serially connected transistors and current sources;
a second signal path segment that comprises a second plurality of serially connected transistors and current sources; and
at least one termination resistor connected to the first and second signal path segments,
wherein the first plurality of serially connected transistors and current sources comprises:
a first current source and a second current source connectable to a reference voltage; and
a first transistor and a second transistor connected between a plurality of input terminals of the equalizer and the first and second current sources,
wherein the first signal path segment further comprises at least one resistor connected between the first and second current sources.