CPC H04L 1/0069 (2013.01) [H04L 5/0048 (2013.01); H04L 5/0051 (2013.01); H04L 25/0224 (2013.01); H04L 27/2675 (2013.01); H04W 4/40 (2018.02); H04B 7/0413 (2013.01)] | 8 Claims |
1. A processor configured to, when executing instructions stored in a memory, perform operations comprising:
receiving data representing a signal comprising a subframe comprising Demodulation Reference Signals (DMRS);
estimating a phase offset between at least two Orthogonal Frequency Division Multiplex (OFDM) or Single Carrier-Frequency Division Multiple Access (SC-FDMA)-symbols in a time domain of the subframe; and
performing a phase offset compensation to the OFDM or SC-FDMA symbols of the subframe based on the phase offset.
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