US 12,068,752 B2
Digital loop filter of low latency and low operation and clock data recovery circuit including the same
Juyun Lee, Suwon-si (KR); Sunggeun Kim, Suwon-si (KR); Hyeonju Lee, Suwon-si (KR); Seuk Son, Suwon-si (KR); Kangjik Kim, Suwon-si (KR); and Jaehyun Park, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 11, 2022, as Appl. No. 17/985,193.
Claims priority of application No. 10-2021-0155148 (KR), filed on Nov. 11, 2021; and application No. 10-2022-0093462 (KR), filed on Jul. 27, 2022.
Prior Publication US 2023/0141322 A1, May 11, 2023
Int. Cl. H03L 7/08 (2006.01); H03L 7/089 (2006.01); H03L 7/093 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/0807 (2013.01) [H03L 7/089 (2013.01); H03L 7/093 (2013.01); H03L 7/0998 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A clock data recovery circuit comprising:
a bang bang phase detector configured to receive data and a clock signal and determine whether a phase of the clock signal leads or lags a phase of the data;
a digital loop filter configured to receive an output of the bang bang phase detector and filter input jitter;
an accumulator configured to accumulate an output from the digital loop filter;
an encoder configured to encode an output of the accumulator to generate a phase interpolation code; and
a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code,
wherein the digital loop filter comprises a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector,
wherein the digital loop filter further comprises a second SDM arithmetic block circuit connected to the first SDM arithmetic block circuit,
wherein the first SDM arithmetic block circuit performs a division operation on the output of the bang bang phase detector using a first SDM coefficient as a divisor, and
wherein the second SDM arithmetic block circuit performs a division operation on an output of the first SDM arithmetic block circuit using a second SDM coefficient as a divisor.