US 12,068,751 B2
Systems and techniques for jitter reduction
Eric J. Stave, Meridian, ID (US); and Tyler J. Gomm, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 29, 2022, as Appl. No. 17/852,657.
Prior Publication US 2024/0007092 A1, Jan. 4, 2024
Int. Cl. G11C 11/4076 (2006.01); G11C 7/22 (2006.01); H03K 5/1534 (2006.01); H03K 5/156 (2006.01); H03K 19/21 (2006.01)
CPC H03K 5/1565 (2013.01) [G11C 7/222 (2013.01); H03K 5/1534 (2013.01); H03K 19/21 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A device, comprising:
a clock input circuit that when in operation receives a clock signal and transmits an internal clock signal based on the clock signal; and
an internal clock generator coupled to the clock input circuit to receive the internal clock signal, wherein the internal clock generator comprises clock adjustment circuitry that when in operation generates a phase controlled internal clock signal having subsequent clock edges based upon a single clock edge of the internal clock signal, wherein the phase controlled internal clock signal comprises a first frequency as a multiple of a second frequency of the internal clock signal, wherein the clock adjustment circuitry comprises:
an edge detector circuit that generates an output clock signal having a third frequency as a multiple of the second frequency with a first duty cycle that differs from a second duty cycle of the internal clock signal; and
a duty cycle corrector comprising a duty cycle adjustment circuit that when in operation adjusts the first duty cycle of output clock signal.