| CPC H03K 3/012 (2013.01) [G06F 1/08 (2013.01); H03K 21/02 (2013.01)] | 11 Claims |
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1. A device, comprising:
a counter circuit configured to count cycles of an input clock signal and to generate an output clock signal periodically based on a cycle count of the input clock signal;
a multi-phase clock generator configured to generate a plurality of multi-phase clock signals from a system clock signal;
a multiplexer circuit coupled to the multi-phase clock generator and configured to provide a multi-phase clock signal selected from the plurality of multi-phase clock signals to the counter circuit as the input clock signal;
one or more D-flip-flops for each of the plurality of multi-phase clock signals are clocked by a respective multi-phase clock signal of the plurality of multi-phase clock signals;
a selection circuit configured to provide a selection signal to the multiplexer circuit periodically to switch the multi-phase clock signal provided to the counter circuit from a current multi-phase clock signal to a next multi-phase clock signal selected from the plurality of multi-phase clock signals; and
each of a D-flip-flop of the one or more D-flip-flops of the current multi-phase clock signal is configured to receive as an input the selection signal that is retimed via a NAND gate, the NAND gate is coupled to an output of the D-flip-flop of the one or more D-flip-flops corresponding to a preceding multi-phase clock signal.
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