US 12,068,554 B2
Dual-path high-speed interconnect PCB layout solution
Paul Danna, Pearland, TX (US); Vincent W. Michna, Houston, TX (US); and Chi Kim Sides, Spring, TX (US)
Assigned to Hewlett Packard Enterprise Development LP, Spring, TX (US)
Filed by Hewlett Packard Enterprise Development LP, Houston, TX (US)
Filed on Jan. 28, 2022, as Appl. No. 17/587,818.
Prior Publication US 2023/0246353 A1, Aug. 3, 2023
Int. Cl. H05K 3/34 (2006.01); H01R 12/70 (2011.01); H01R 12/71 (2011.01); H01R 43/02 (2006.01)
CPC H01R 12/716 (2013.01) [H01R 12/707 (2013.01); H01R 43/0256 (2013.01); H05K 3/3405 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A dual-path signal interconnect on a printed circuit board (PCB), comprising:
a first signal trace for carrying high-speed electrical signals;
a first solder pad having a first size positioned above and connected to the first signal trace;
a second solder pad having a second size positioned above and connected to the first signal trace, wherein the second solder pad separate from the first solder pad by a first gap; and
a third solder pad having a third size, wherein the third solder pad separate from the second solder pad by a second gap and is connected to a second signal trace;
wherein the first and second solder pads are to allow a pin of an external connector to be soldered simultaneously to the first and second solder pads, such that, when the pin of the external connector is soldered, the high-speed electrical signals are routed to the external connector; and
wherein the second and third solder pads are to allow a conductor to be soldered simultaneously to the second and third solder pads, such that, when the conductor is soldered, the high-speed electrical signals are routed to the second signal trace.