US 12,068,428 B2
Vertical solid state devices
Gholamreza Chaji, Waterloo (CA); Ehsanollah Fathi, Waterloo (CA); and Hossein Zamani Siboni, Waterloo (CA)
Assigned to VueReal Inc., Waterloo (CA)
Filed by VueReal Inc., Waterloo (CA)
Filed on Aug. 20, 2020, as Appl. No. 16/998,455.
Application 16/998,455 is a continuation of application No. 15/389,728, filed on Dec. 23, 2016, granted, now 10,784,398.
Claims priority of application No. 2916291 (CA), filed on Dec. 24, 2015; and application No. 2924157 (CA), filed on Mar. 18, 2016.
Prior Publication US 2020/0381582 A1, Dec. 3, 2020
Int. Cl. H01L 33/00 (2010.01); H01L 27/15 (2006.01); H01L 33/62 (2010.01)
CPC H01L 33/0037 (2013.01) [H01L 27/153 (2013.01); H01L 33/62 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A method of creating an array of current driven devices in a continuous semiconductor bulk by resistance engineering, the resistance engineering including:
forming device layers on a substrate;
forming an array of contact pads on top of the device layers;
forming a metal-insulator-semiconductor structure around the contact pads;
after the forming the device layers, the array of contact pads, and the metal-insulator-semiconductor structure, manipulating a resistance of an area of a conductive top layer between adjacent contact pads within the continuous semiconductor bulk to limit lateral current flow components; and
after the forming the device layers, the array of contact pads, and the metal-insulator-semiconductor structure, biasing the metal-insulator-semiconductor structure to force current vertically in the device layers.