US 12,068,414 B2
Interface profile control in epitaxial structures for semiconductor devices
Winnie Victoria Wei-Ning Chen, Zhubei (TW); Pang-Yen Tsai, Jhu-bei (TW); and Yasutoshi Okuno, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd.
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 6, 2022, as Appl. No. 17/858,969.
Application 17/858,969 is a continuation of application No. 16/941,035, filed on Jul. 28, 2020, granted, now 11,417,764.
Claims priority of provisional application 62/967,226, filed on Jan. 29, 2020.
Prior Publication US 2022/0352370 A1, Nov. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7842 (2013.01) [H01L 21/02304 (2013.01); H01L 21/02507 (2013.01); H01L 29/0665 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a fin structure on a substrate;
forming a superlattice structure on the fin structure, comprising first and second nanostructured layers;
forming an opening in the superlattice structure and in the fin structure, wherein first, second, and third surfaces of the first nanostructured layers, second nanostructured layers, and fin structure, respectively, are exposed within the opening;
modifying the first surfaces of the first nanostructured layers to curve a profile of the first surfaces;
depositing first, second, and third passivation layers on the first, second, and third surfaces, respectively, wherein the first, second, and third passivation layers are different from each other; and
forming an epitaxial source/drain (S/D) region on the superlattice structure.