	US 12,068,405 B2
	Semiconductor device and manufacturing method thereof
Sheng-Kai Su, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD, Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Jun. 28, 2022, as Appl. No. 17/852,079.
Application 17/852,079 is a division of application No. 16/656,210, filed on Oct. 17, 2019, granted, now 11,380,785.
Prior Publication US 2022/0336647 A1, Oct. 20, 2022
Int. Cl. H01L 29/76 (2006.01); H01L 29/24 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)

CPC H01L 29/7606 (2013.01) [H01L 29/24 (2013.01); H01L 29/66969 (2013.01); H01L 29/7851 (2013.01)]

20 Claims

1. A method, comprising:

forming a semiconductor fin protruding above a substrate;

forming a first 2D material layer across the semiconductor fin;

depositing a gate material layer over the first 2D material layer;

etching the gate material layer and the first 2D material layer to form a gate structure and a patterned first 2D material layer under the gate structure;

laterally growing a second 2D material layer, by using a sidewall of the patterned first 2D material layer as a base layer, along a surface of the semiconductor fin, such that the second 2D material layer and the patterned first 2D material layer have substantially a same thickness;

after laterally growing the second 2D material layer, forming gate spacers respectively on opposite sidewalls of the gate structure; and

after forming the gate spacers, forming a third 2D material layer on the second 2D material layer until a combination of the third 2D material layer and the second 2D material layer comprises at least three or more monolayers of PtSe₂.