US 12,068,397 B2
Semiconductor structure and fabrication method thereof
Xiang Hu, Shanghai (CN)
Assigned to Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai (CN); and Semiconductor Manufacturing International (Beijing) Corporation, Beijing (CN)
Filed by Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai (CN); and Semiconductor Manufacturing International (Beijing) Corporation, Beijing (CN)
Filed on May 18, 2023, as Appl. No. 18/198,944.
Application 18/198,944 is a continuation of application No. 17/220,210, filed on Apr. 1, 2021, granted, now 11,688,798.
Claims priority of application No. 202010339107.4 (CN), filed on Apr. 26, 2020.
Prior Publication US 2023/0290867 A1, Sep. 14, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/6681 (2013.01) [H01L 21/823431 (2013.01); H01L 27/0924 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate, wherein the substrate includes a first region and a second region adjacent to the first region;
a first gate structure and first source-drain doped layers, wherein the first gate structure is formed over the first region, and the first source-drain doped layers are formed in the first region of the substrate on both sides of the first gate structure, respectively;
a second gate structure and second source-drain doped layers, wherein the second gate structure is formed over the second region, and the second source-drain doped layers are formed in the second region of the substrate on both sides of the second gate structure, respectively;
a first protection layer, formed over the second gate structure;
a first conductive structure, formed over a first source-drain doped layer of the source-drain doped layers, wherein the first conductive structure is also formed on the first gate structure, a top surface of the first conductive structure is lower than a top surface of the first protection layer; and
an isolation layer, formed over the first conductive structure, a top surface of the isolation layer over the first conductive structure being coplanar with the top surface of the first protection layer over second gate structure.