	US 12,068,393 B2
	Etching back and selective deposition of metal gate
Peng-Soon Lim, Kluang (MY); Cheng-Lung Hung, Hsinchu (TW); Mao-Lin Huang, Hsinchu (TW); and Weng Chang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 18, 2022, as Appl. No. 17/663,979.
Application 17/663,979 is a continuation of application No. 16/685,672, filed on Nov. 15, 2019, granted, now 11,380,774.
Application 16/685,672 is a continuation of application No. 15/621,518, filed on Jun. 13, 2017, granted, now 10,879,370, issued on Dec. 29, 2020.
Claims priority of provisional application 62/434,889, filed on Dec. 15, 2016.
Prior Publication US 2022/0278224 A1, Sep. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/51 (2006.01)

CPC H01L 29/66545 (2013.01) [H01L 21/28026 (2013.01); H01L 29/42376 (2013.01); H01L 29/4966 (2013.01); H01L 29/66583 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/0673 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/66439 (2013.01); H01L 29/665 (2013.01)]

20 Claims

1. A method comprising:

removing a dummy gate stack in a dielectric layer to form a trench between gate spacers;

forming a gate dielectric layer extending into the trench;

forming a metal layer extending into the trench and over the gate dielectric layer;

forming a protection layer extending into the trench and over the metal layer;

etching back the protection layer until a top surface of a portion of the protection layer is lower than a top surface of the dielectric layer;

etching first portions of the gate dielectric layer and second portions of the metal layer in the trench, wherein the protection layer is used as an etching mask during the etching, wherein after the etching, a first top end of the gate dielectric layer is lower than second top ends of the gate spacers, and higher than third top ends of the metal layer; and

after the metal layer is etched, depositing a conductive layer in the trench and on the metal layer, wherein the conductive layer is selectively deposited on the metal layer.