US 12,068,389 B2
Semiconductor device including gas spacers and method of manufacture
Yen-Ting Chen, Taichung (TW); Wei-Yang Lee, Taipei (TW); Feng-Cheng Yang, Zhudong Township (TW); and Yen-Ming Chen, Chu-Pei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 13, 2023, as Appl. No. 18/300,192.
Application 18/300,192 is a continuation of application No. 17/121,385, filed on Dec. 14, 2020, granted, now 11,631,746.
Application 17/121,385 is a continuation of application No. 16/371,498, filed on Apr. 1, 2019, granted, now 10,868,130, issued on Dec. 15, 2020.
Claims priority of provisional application 62/753,348, filed on Oct. 31, 2018.
Prior Publication US 2023/0253474 A1, Aug. 10, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/49 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/764 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/4991 (2013.01) [H01L 21/02164 (2013.01); H01L 21/02167 (2013.01); H01L 21/0217 (2013.01); H01L 21/31116 (2013.01); H01L 21/764 (2013.01); H01L 29/0847 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a gate stack over a semiconductor substrate;
forming a gate spacer on sidewalls of the gate stack;
epitaxially growing source/drain regions on opposite sides of the gate stack;
depositing a contact etch stop layer (CESL) over the source/drain regions;
depositing an interlayer dielectric layer (ILD) over the CESL;
planarizing the CESL, the ILD, the gate stack, the gate spacer;
removing at least a portion of the gate spacer to form an opening; and
depositing a dielectric layer sealing the opening and defining a gaseous spacer.