CPC H01L 29/4991 (2013.01) [H01L 21/02164 (2013.01); H01L 21/02167 (2013.01); H01L 21/0217 (2013.01); H01L 21/31116 (2013.01); H01L 21/764 (2013.01); H01L 29/0847 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] | 20 Claims |
1. A method comprising:
forming a gate stack over a semiconductor substrate;
forming a gate spacer on sidewalls of the gate stack;
epitaxially growing source/drain regions on opposite sides of the gate stack;
depositing a contact etch stop layer (CESL) over the source/drain regions;
depositing an interlayer dielectric layer (ILD) over the CESL;
planarizing the CESL, the ILD, the gate stack, the gate spacer;
removing at least a portion of the gate spacer to form an opening; and
depositing a dielectric layer sealing the opening and defining a gaseous spacer.
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