US 12,068,383 B2
Wrap around silicide for FinFETs
Kuo-Cheng Chiang, Zhubei (TW); Chi-Wen Liu, Hsinchu (TW); and Ying-Keung Leung, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 18, 2022, as Appl. No. 17/813,110.
Application 15/221,123 is a division of application No. 14/739,294, filed on Jun. 15, 2015, granted, now 9,418,897, issued on Aug. 16, 2016.
Application 17/813,110 is a continuation of application No. 16/883,227, filed on May 26, 2020, granted, now 11,437,479.
Application 16/883,227 is a continuation of application No. 16/236,783, filed on Dec. 31, 2018, granted, now 10,665,718, issued on May 26, 2020.
Application 16/236,783 is a continuation of application No. 15/859,863, filed on Jan. 2, 2018, granted, now 10,170,365, issued on Jan. 1, 2019.
Application 15/859,863 is a continuation of application No. 15/221,123, filed on Jul. 27, 2016, granted, now 9,876,108, issued on Jan. 23, 2018.
Prior Publication US 2022/0352329 A1, Nov. 3, 2022
Int. Cl. H01L 29/417 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 12/00 (2023.01)
CPC H01L 29/41791 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 21/823481 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/845 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 27/1211 (2013.01); H01L 29/0649 (2013.01); H01L 29/41725 (2013.01); H01L 29/41783 (2013.01); H01L 29/456 (2013.01); H01L 29/6656 (2013.01); H01L 29/66575 (2013.01); H01L 29/66636 (2013.01); H01L 29/66772 (2013.01); H01L 29/66795 (2013.01); H01L 29/7831 (2013.01); H01L 29/785 (2013.01); H10B 12/056 (2023.02); H01L 29/66545 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
a dielectric isolation region extending into the substrate;
a semiconductor strip between and contacting opposing portions of the dielectric isolation region;
a gate structure on the substrate;
a first spacer adjacent to and directly contacting the gate structure, wherein the first spacer comprises silicon carbo-nitride (SiCN), and the first spacer has an L-shape;
a second spacer adjacent to and directly contacting the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN), and wherein the second spacer comprises;
a vertical-and-straight inner edge; and
an outer edge comprising a vertical-and-straight portion;
a source/drain region adjacent to two sides of the second spacer, wherein the source/drain region overlaps the semiconductor strip, and wherein the source/drain region comprises:
a first vertical-and-straight sidewall; and
a second vertical-and-straight sidewall parallel to the first vertical-and-straight sidewall, wherein the source/drain region is wider than the semiconductor strip; and
a top dielectric layer over and contacting a top surface of the dielectric isolation region, wherein the top dielectric layer comprises SiCN, wherein the top dielectric layer further extends directly underlying the source/drain region.