US 12,068,375 B2
Nitride semiconductor device
Daisuke Shibata, Kyoto (JP); Satoshi Tamura, Osaka (JP); and Naohiro Tsurumi, Kyoto (JP)
Assigned to PANASONIC HOLDINGS CORPORATION, Osaka (JP)
Appl. No. 17/763,558
Filed by Panasonic Corporation, Osaka (JP)
PCT Filed Sep. 25, 2020, PCT No. PCT/JP2020/036481
§ 371(c)(1), (2) Date Mar. 24, 2022,
PCT Pub. No. WO2021/079686, PCT Pub. Date Apr. 29, 2021.
Claims priority of application No. 2019-193095 (JP), filed on Oct. 24, 2019.
Prior Publication US 2022/0376055 A1, Nov. 24, 2022
Int. Cl. H01L 29/778 (2006.01); H01L 21/8232 (2006.01); H01L 29/20 (2006.01); H01L 29/417 (2006.01); H01L 29/808 (2006.01); H01L 29/812 (2006.01); H01L 29/861 (2006.01)
CPC H01L 29/2003 (2013.01) [H01L 21/8232 (2013.01); H01L 29/41758 (2013.01); H01L 29/778 (2013.01); H01L 29/808 (2013.01); H01L 29/812 (2013.01); H01L 29/861 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A nitride semiconductor device including a vertical transistor and a vertical diode, the nitride semiconductor device comprising:
a substrate;
a first nitride semiconductor layer of a first conductivity type above the substrate;
a second nitride semiconductor layer of a second conductivity type above the first nitride semiconductor layer, the second conductivity type being different from the first conductivity type;
a first opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer;
a second opening provided away from the first opening and penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer;
an electron transport layer and an electron supply layer provided, in stated order from a substrate side, along an inner face of each of the first opening and the second opening and above the second nitride semiconductor layer;
a gate electrode of the vertical transistor above the electron supply layer and covering the first opening;
an anode electrode of the vertical diode above the electron supply layer and covering the second opening;
a third opening provided between the first opening and the second opening in a plan view and penetrating through the electron supply layer and the electron transport layer to the second nitride semiconductor layer;
a source electrode of the vertical transistor connected to the second nitride semiconductor layer and a portion of each of the electron supply layer and the electron transport layer on a first opening side, in the third opening;
a drain electrode of the vertical transistor provided on a side of the substrate facing away from the first nitride semiconductor layer, at a position where the drain electrode overlaps the gate electrode in a plan view; and
a cathode electrode of the vertical diode on the side of the substrate facing away from the first nitride semiconductor layer, at a position where the cathode electrode overlaps the anode electrode in a plan view,
wherein the anode electrode and the source electrode are electrically connected, and
the cathode electrode and the drain electrode are electrically connected.