US 12,068,371 B2
Method for FinFET LDD doping
Chun Hsiung Tsai, Hsinchu County (TW); Ya-Yun Cheng, Taichung (TW); Shahaji B. More, Hsinchu (TW); Cheng-Yi Peng, Taipei (TW); Wei-Yang Lee, Taipei (TW); Kuo-Feng Yu, Hsinchu County (TW); Yen-Ming Chen, Hsin-Chu County (TW); and Jian-Hao Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 26, 2021, as Appl. No. 17/240,027.
Application 16/421,036 is a division of application No. 15/882,285, filed on Jan. 29, 2018, granted, now 10,396,156, issued on Aug. 27, 2019.
Application 17/240,027 is a continuation of application No. 16/421,036, filed on May 23, 2019, granted, now 10,991,800.
Prior Publication US 2021/0242310 A1, Aug. 5, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/306 (2006.01); H01L 29/06 (2006.01); H01L 29/165 (2006.01); H01L 29/167 (2006.01); H01L 29/36 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0847 (2013.01) [H01L 21/0217 (2013.01); H01L 21/02636 (2013.01); H01L 21/26513 (2013.01); H01L 21/26586 (2013.01); H01L 21/30604 (2013.01); H01L 29/0649 (2013.01); H01L 29/167 (2013.01); H01L 29/36 (2013.01); H01L 29/6656 (2013.01); H01L 29/66575 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/7833 (2013.01); H01L 29/7851 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/266 (2013.01); H01L 29/165 (2013.01); H01L 29/66545 (2013.01); H01L 29/7848 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
an isolation structure over the substrate;
a fin over the substrate and the isolation structure;
a gate structure engaging a first portion of the fin;
first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin;
source/drain (S/D) features adjacent to the first sidewall spacers; and
second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features, wherein the second sidewall spacers include silicon oxide, silicon nitride, or silicon oxynitride, wherein the second sidewall spacers and the second portion of the fin include a same dopant, wherein the dopant includes phosphorus.