US 12,068,370 B2
Semiconductor device structure and methods of forming the same
Chi-Yi Chuang, Hsinchu (TW); Cheng-Ting Chung, Hsinchu (TW); Hou-Yu Chen, Hsinchu (TW); and Kuan-Lun Cheng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Apr. 28, 2023, as Appl. No. 18/141,077.
Application 18/141,077 is a continuation of application No. 17/184,877, filed on Feb. 25, 2021, granted, now 11,652,140.
Prior Publication US 2023/0268391 A1, Aug. 24, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10B 10/00 (2023.01)
CPC H01L 29/0665 (2013.01) [H01L 29/401 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H10B 10/125 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first device layer over a first substrate;
depositing a first dielectric layer over the first device layer;
forming a first stack of layers over a second substrate;
depositing a second dielectric layer on the first stack of layers;
flipping over the second substrate;
bonding the first dielectric layer to the second dielectric layer;
removing the second substrate;
forming a second device layer over the first device layer, wherein the first device layer comprises a first transistor, the second device layer comprises a second transistor, and the first and second transistors share a gate electrode layer.