US 12,068,361 B2
Semiconductor structure with stacked capacitors
BingYu Zhu, Hefei (CN); Hai-Han Hung, Hefei (CN); and Yin-Kuei Yu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Aug. 13, 2021, as Appl. No. 17/401,523.
Application 17/401,523 is a continuation of application No. PCT/CN2021/100905, filed on Jun. 18, 2021.
Claims priority of application No. 202010959932.4 (CN), filed on Sep. 14, 2020.
Prior Publication US 2022/0085149 A1, Mar. 17, 2022
Int. Cl. H10B 12/00 (2023.01); H01L 27/08 (2006.01); H01L 49/02 (2006.01)
CPC H01L 28/82 (2013.01) [H01L 27/0805 (2013.01); H01L 28/91 (2013.01); H10B 12/01 (2023.02); H10B 12/02 (2023.02); H10B 12/315 (2023.02)] 7 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a first capacitor located on the substrate, wherein the first capacitor comprises a first bottom electrode, a first dielectric layer and a first top electrode, the first bottom electrode is of a columnar structure, the first dielectric layer covers the first bottom electrode, and the first top electrode is located on one surface of the first dielectric layer away from the first bottom electrode; and
a second capacitor, located above the first capacitor, wherein the second capacitor comprises a second bottom electrode being of a concave structure and electrically connected with the first bottom electrode, a second dielectric layer filling and covering the second bottom electrode, and a second top electrode;
wherein the second dielectric layer is located between the second bottom electrode and the second top electrode, and the second dielectric layer is further located between the second bottom electrodes of adjacent second capacitors,
wherein the semiconductor structure further comprises a first supporting layer, a second supporting layer and a third supporting layer, the first supporting layer is located at a periphery of a bottom of the first bottom electrode, and the second supporting layer is located at a periphery of a top of the first bottom electrode, the third supporting layer is located at a periphery of a bottom of the second bottom electrode, and part of the third supporting layer is disposed in the second supporting layer such that a line extending parallel to a top surface of the substrate intersects both the part of the third supporting layer and the second supporting layer, and
wherein the second dielectric layer fully fills a partial space between the second bottom electrodes of the adjacent second capacitors, and the partial space is away from the third supporting layer.