US 12,068,339 B2
Imaging device and electronic device
Yoshiyuki Kurokawa, Sagamihara (JP); and Tatsunori Inoue, Isehara (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 16/606,906
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
PCT Filed Apr. 20, 2018, PCT No. PCT/IB2018/052743
§ 371(c)(1), (2) Date Oct. 21, 2019,
PCT Pub. No. WO2018/203169, PCT Pub. Date Nov. 8, 2018.
Claims priority of application No. 2017-091864 (JP), filed on May 2, 2017.
Prior Publication US 2020/0382730 A1, Dec. 3, 2020
Int. Cl. H01L 27/146 (2006.01); G06N 3/045 (2023.01); G06N 3/088 (2023.01); G06V 10/44 (2022.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H04N 25/76 (2023.01); H10B 99/00 (2023.01)
CPC H01L 27/14609 (2013.01) [G06N 3/045 (2023.01); G06N 3/088 (2013.01); G06V 10/454 (2022.01); H01L 27/1207 (2013.01); H01L 27/1211 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 29/78648 (2013.01); H01L 29/7869 (2013.01); H04N 25/76 (2023.01); H10B 99/00 (2023.02)] 9 Claims
OG exemplary drawing
 
1. An electronic device comprising:
an imaging device; and
a peripheral circuit, wherein the imaging device comprises:
an imaging portion comprising pixels arranged in n rows and m columns, wherein n and m are each an integer greater than or equal to 1;
a circuit including a shift register, the shift register comprising a plurality of retention circuits, an input terminal, and a plurality of output terminals; and
an encoder comprising a memory cell array and a first circuit that forms a first neural network,
wherein the peripheral circuit comprises:
a decoder comprising a second circuit that forms a second neural network; and
an image processing circuit,
wherein the imaging portion is configured to generate first image data by imaging and input the first image data to the input terminal of the shift register pixel by pixel,
wherein the output terminals of the shift register are electrically connected to the memory cell array,
wherein the first circuit comprises a plurality of first programmable logic elements and a plurality of first programmable switches,
wherein the first circuit is configured to conduct feature extraction on the first image data to generate second image data by sequentially switching connection state between the plurality of first programmable logic elements and the plurality of first programmable switches,
wherein the second circuit is electrically connected to the first circuit and configured to conduct decompression processing on the second image data to generate third image data,
wherein the image processing circuit is electrically connected to the second circuit,
wherein a number of wirings electrically connecting the first circuit and the second circuit is smaller than a number of wirings electrically connecting the second circuit and the image processing circuit,
wherein the first neural network is configured to perform convolution processing using a weight filter and the first image data, and
wherein the memory cell array is configured to store a filter value of the weight filter.