US 12,068,329 B2
Semiconductor device and method for manufacturing the same
Shunpei Yamazaki, Setagaya (JP); Hidekazu Miyairi, Isehara (JP); Akiharu Miyanaga, Hadano (JP); Kengo Akimoto, Atsugi (JP); and Kojiro Shiraishi, Isehara (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Dec. 23, 2021, as Appl. No. 17/560,479.
Application 17/560,479 is a continuation of application No. 16/233,358, filed on Dec. 27, 2018, granted, now 11,296,121.
Application 16/233,358 is a continuation of application No. 15/263,997, filed on Sep. 13, 2016, abandoned.
Application 15/263,997 is a continuation of application No. 13/547,377, filed on Jul. 12, 2012, granted, now 9,496,406, issued on Nov. 15, 2016.
Application 13/547,377 is a continuation of application No. 12/511,291, filed on Jul. 29, 2009, granted, now 8,624,237, issued on Jan. 7, 2014.
Claims priority of application No. 2008-197147 (JP), filed on Jul. 31, 2008.
Prior Publication US 2022/0115412 A1, Apr. 14, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/12 (2006.01); H01L 29/24 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); G02F 1/1333 (2006.01); G02F 1/1335 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G09G 3/36 (2006.01); H10K 59/121 (2023.01)
CPC H01L 27/1225 (2013.01) [H01L 29/247 (2013.01); H01L 29/66969 (2013.01); H01L 29/78618 (2013.01); H01L 29/78648 (2013.01); H01L 29/7869 (2013.01); H01L 29/78693 (2013.01); H01L 29/78696 (2013.01); G02F 1/133345 (2013.01); G02F 1/133528 (2013.01); G02F 1/134336 (2013.01); G02F 1/13439 (2013.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G02F 2201/123 (2013.01); G09G 3/3674 (2013.01); G09G 2310/0286 (2013.01); H10K 59/1213 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a gate electrode layer comprising copper;
a gate insulating layer over the gate electrode layer;
an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer comprising a channel formation region of a transistor;
a first layer over the oxide semiconductor layer;
a second layer over the oxide semiconductor layer;
a first conductive layer electrically connected to the oxide semiconductor layer through the first layer; and
a second conductive layer electrically connected to the oxide semiconductor layer through the second layer,
wherein the first conductive layer is configured to function as one of a source electrode layer and a drain electrode layer,
wherein the second conductive layer is configured to function as the other of the source electrode layer and the drain electrode layer,
wherein, in a cross-sectional view in a channel length direction of the transistor:
an edge of the oxide semiconductor layer is provided in a first region beyond an edge of the first layer,
the edge of the first layer on the first region side is provided in a region beyond an edge of the first conductive layer, and
a film thickness of the oxide semiconductor layer in the first region is smaller than the film thickness of the oxide semiconductor layer in a region overlapping the first layer.