US 12,068,325 B2
Optimization of semiconductor cell of vertical field effect transistor (VFET)
Jung Ho Do, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 17, 2023, as Appl. No. 18/155,386.
Application 18/155,386 is a continuation of application No. 16/941,042, filed on Jul. 28, 2020, granted, now 11,581,338.
Claims priority of provisional application 62/910,635, filed on Oct. 4, 2019.
Prior Publication US 2023/0178558 A1, Jun. 8, 2023
Int. Cl. H01L 27/118 (2006.01)
CPC H01L 27/11807 (2013.01) [H01L 2027/11831 (2013.01); H01L 2027/11851 (2013.01); H01L 2027/11875 (2013.01); H01L 2027/11881 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A vertical field effect transistor (VFET) cell implementing a scan flip-flop with a reset input comprising a plurality of circuits over 1st through 24th gate grids, which are consecutively formed and evenly spaced in the VFET cell,
wherein the 1st gate grid provides a one-fin scan inverter,
wherein the 2nd through 6th gate grids provide a scan stage circuit configured to receive a scan input signal, a data signal, a scan enable signal, and an inverted scan enable signal,
wherein the 7th through 11th gate grids provide a master latch,
wherein the 12th and 13th gate grids provide a two-fin clock inverter,
wherein the 14th gate grid provides an output circuit comprising a one-fin inverter,
wherein the 15th through 17th gate grids provide a slave data path circuit configured to receive a reset signal for the master latch,
wherein the 18th and 19th gate grids provide a master data path circuit configured to receive the reset signal for a slave latch, and
wherein the 20th through 24th gate grids provide the slave latch.