US 12,068,321 B2
Semiconductor devices
Sungmin Kim, Incheon (KR); and Soonmoon Jung, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 5, 2023, as Appl. No. 18/347,023.
Application 18/347,023 is a division of application No. 17/506,785, filed on Oct. 21, 2021, granted, now 11,728,343.
Application 17/506,785 is a division of application No. 16/849,238, filed on Apr. 15, 2020, granted, now 11,171,136, issued on Nov. 9, 2021.
Claims priority of application No. 10-2019-0094521 (KR), filed on Aug. 2, 2019.
Prior Publication US 2023/0343786 A1, Oct. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 21/18 (2006.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/0922 (2013.01) [H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/187 (2013.01); H01L 21/28088 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/82345 (2013.01); H01L 21/823475 (2013.01); H01L 29/0673 (2013.01); H01L 29/1608 (2013.01); H01L 29/161 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/4908 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78684 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first transistor on a substrate, the first transistor including a first gate structure, first source/drain layers at respective opposite sides of the first gate structure, and first semiconductor patterns spaced apart from each other in a vertical direction that is substantially perpendicular to an upper surface of the substrate, and each of the first semiconductor patterns extending through the first gate structure and contacting the first source/drain layers;
a division pattern on the first transistor, the division pattern including an insulating material;
a second transistor on the division pattern, the second transistor including a second gate structure, second source/drain layers at respective opposite sides of the second gate structure, and second semiconductor patterns spaced apart from each other in the vertical direction, and each of the second semiconductor patterns extending through the second gate structure and contacting the second source/drain layers;
a first via extending in the vertical direction and contacting a first one of the first source/drain layers;
a second via extending in the vertical direction and contacting a first one of the second source/drain layers; and
a connection plug extending in the vertical direction through an upper portion of a second one of the first source/drain layers, the division pattern, and a second one of the second source/drain layers,
wherein a width in a horizontal direction substantially parallel to the upper surface of the substrate of the first via decreases from a bottom toward a top thereof, a width in the horizontal direction of the second via increases from a bottom toward a top thereof, and a width in the horizontal direction of the connection plug increases from a bottom toward a top thereof.