US 12,068,318 B2
Method of forming epitaxial features
Ming-Yang Huang, Hsinchu (TW); Yung Feng Chang, Hsinchu (TW); Tung-Heng Hsieh, Hsinchu County (TW); and Bao-Ru Young, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 8, 2023, as Appl. No. 18/446,185.
Application 18/446,185 is a division of application No. 17/377,705, filed on Jul. 16, 2021, granted, now 11,855,081.
Prior Publication US 2024/0030220 A1, Jan. 25, 2024
Int. Cl. H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 29/6656 (2013.01); H01L 29/6681 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a device region comprising:
a plurality of active regions extending lengthwise along a first direction, each of the plurality of active regions comprising a plurality of channel regions interleaved by a plurality of source/drain regions,
a plurality of gate structures extending lengthwise along a second direction perpendicular to the first direction and disposed over the plurality of channel regions, and
a plurality of source/drain features disposed over the plurality of source/drain features; and
two terminal end portions sandwiched between the device region along the second direction, each of the two terminal end portions comprising:
terminal end portions of the plurality of gate structures,
wherein a gate spacer disposed along each of the plurality of gate structures includes a first portion in the device region and a second portion in the two terminal end portion,
wherein the first portion comprises a first thickness and the second portion comprises a second thickness greater than the first thickness.