US 12,068,314 B2
Fabrication of gate-all-around integrated circuit structures having adjacent island structures
Leonard P. Guler, Hillsboro, OR (US); William Hsu, Hillsboro, OR (US); Biswajeet Guha, Hillsboro, OR (US); Martin Weiss, Portland, OR (US); Apratim Dhar, Portland, OR (US); William T. Blanton, Cornelius, OR (US); John H. Irby, IV, Hillsboro, OR (US); James F. Bondi, Beaverton, OR (US); Michael K. Harper, Hillsboro, OR (US); Charles H. Wallace, Portland, OR (US); Tahir Ghani, Portland, OR (US); Benedict A. Samuel, Hillsboro, OR (US); and Stefan Dickert, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 18, 2020, as Appl. No. 17/026,047.
Prior Publication US 2022/0093589 A1, Mar. 24, 2022
Int. Cl. H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 29/42392 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01)] 28 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a semiconductor island on a semiconductor substrate;
a first vertical arrangement of horizontal nanowires above a first fin protruding from the semiconductor substrate, a channel region of the first vertical arrangement of horizontal nanowires electrically isolated from the fin; and
a second vertical arrangement of horizontal nanowires above a second fin protruding from the semiconductor substrate, a channel region of the second vertical arrangement of horizontal nanowires electrically isolated from the second fin, wherein the semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires, and wherein the semiconductor island has an uppermost surface above an uppermost surface of the first vertical arrangement of horizontal nanowires and above an uppermost surface of the second vertical arrangement of horizontal nanowires.