US 12,068,300 B2
Chip-on-wafer-on-substrate package with improved yield
Chia-Wei Chang, Taipei (TW); Ju-Min Chen, Tainan (TW); Jyun-Lin Wu, Hsinchu (TW); and Yao-Chun Chuang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 25, 2022, as Appl. No. 17/680,523.
Prior Publication US 2023/0275077 A1, Aug. 31, 2023
Int. Cl. H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/18 (2013.01) [H01L 23/3157 (2013.01); H01L 23/49816 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/562 (2013.01); H01L 25/50 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A chip-on-wafer-on-substrate (CoWoS) semiconductor assembly comprising:
a chip-on-wafer (CoW) sub-assembly comprising a plurality of integrated circuit (IC) dies mounted on a front side of an interposer having through-vias passing through the interposer with ends of the through-vias exposed at a backside of the interposer opposite the front side of the interposer;
a package substrate having a front side comprising a top metallization stack and a backside opposite the front side comprising a bottom metallization stack; and
bonding bumps connecting the backside of the interposer and the front side of the package substrate with the bonding bumps providing electrical connections between the ends of the through-vias exposed at the backside of the interposer and the top metallization stack of the package substrate;
wherein a total metal thickness of the top metallization stack of the package substrate is greater than a total metal thickness of the bottom metallization stack of the package substrate.