CPC H01L 25/18 (2013.01) [H01L 23/481 (2013.01); H01L 23/528 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/09 (2013.01); H01L 25/50 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/09181 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] | 14 Claims |
1. A semiconductor device, comprising:
a first chip including a first substrate and a logic circuit provided on an upper surface of the first substrate; a second chip provided above the first chip and bonded to the first chip, the second chip including a first wiring layer, a memory cell array provided above the first wiring layer, a second substrate provided above the memory cell array, and a first plug provided between the second substrate and the first wiring layer and extending in a first direction;
a plurality of metal pads provided on a bonding surface of the first chip and the second chip and electrically coupling the logic circuit to the memory cell array;
a bonding pad provided above the second substrate; and
a second plug extending through the second substrate in the first direction and coupling the bonding pad to the first plug, wherein
an upper end of the first plug has a first width in a second direction crossing the first direction,
the first width is smaller than a maximum width of the first plug in the second direction,
an upper end of the second plug has a second width in the second direction, and
the first width is smaller the second width.
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