US 12,068,290 B2
Power semiconductor module with low inductance gate crossing
Arne Schroeder, Bern (CH); Slavo Kicin, Zürich (CH); Fabian Mohn, Ennetbaden (CH); and Juergen Schuderer, Zürich (CH)
Assigned to Hitachi Energy Ltd, Zürich (CH)
Appl. No. 17/611,305
Filed by Hitachi Energy Ltd, Zürich (CH)
PCT Filed Apr. 2, 2020, PCT No. PCT/EP2020/059408
§ 371(c)(1), (2) Date Nov. 15, 2021,
PCT Pub. No. WO2020/229052, PCT Pub. Date Nov. 19, 2020.
Claims priority of application No. 19174478 (EP), filed on May 14, 2019.
Prior Publication US 2022/0238493 A1, Jul. 28, 2022
Int. Cl. H01L 25/07 (2006.01); H01L 23/00 (2006.01); H01L 23/373 (2006.01); H01L 23/538 (2006.01)
CPC H01L 25/072 (2013.01) [H01L 23/3735 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/32 (2013.01); H01L 24/49 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/49111 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/19107 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A power semiconductor module, comprising:
a main substrate with a main conductive layer separated into conductive areas;
a plurality of power semiconductor chips, wherein each power semiconductor chip has a first power electrode, a second power electrode, and a gate electrode, wherein each power semiconductor chip is bonded to the main conductive layer with the first power electrode and wherein a first group of the power semiconductor chips is connected in parallel via the second power electrodes and a second group of the power semiconductor chips is connected in parallel via the second power electrodes;
a first insulation layer attached to the main conductive layer;
a first conductive layer provided on the first insulation layer, wherein the first conductive layer provides a first gate conductor area electrically connected to the gate electrodes of the first group and a first auxiliary emitter conductor area electrically connected to power electrodes of the first group;
a second insulation layer attached to the first conductive layer; and
a second conductive layer provided on the second insulation layer, wherein the second conductive layer provides a second gate conductor area electrically connected to the gate electrodes of the second group and a second auxiliary emitter conductor area electrically connected to power electrodes of the second group;
wherein the main conductive layer, the first insulation layer, the first conductive layer, the second insulation layer and the second conductive layer are stacked with respect to each other.